In this work, we present a complete design implementation and characterization of an analog silicon photomultiplier (SiPM) with integrated time-to-digital converter (TDC).
The combination of a photodetector together with on-chip readout circuitry in close proximity enables system-level advantages such as internal parasitic reduction for better single- photon timing resolution (SPTR), but also overall simplicity and compactness. The system comprises a C-Series analog SiPM developed by SensL, a TDC, and a comparator. The design was implemented in 0.35μm CMOS technology. The proposed analog SiPM features 48% photon detection efficiency (PDE) at 420nm wavelength and +6.0V excess bias. Thanks to the small size of the electronics, the overall sensor fill factor is 75% and its sensitive area is 3×3mm2. The SiPM fast output, which is a specialized terminal for fast timing output signals, has a parasitic capacitance of about 12pF. The TDC is a multi-path-gated ring oscillator with a 6-bit coarse counter and 9-bit phase detector. Post-layout simulation results indicate a 65ps LSB in typical corner with differential non-linearity (DNL) and integral non- linearity (INL) of ±0.55LSB and ±1LSB, respectively. The comparator is composed of two preamplifier stages followed by a complementary self-biased differential amplifier stage (CSDA), directly coupled to the fast output through a capacitor. Post- layout simulation indicates 48V/ns slew rate and a preamplifier stage bandwidth of ~1GHz. The comparator power consumption without the additional preamplifier stage is 198μW. The chip is currently under fabrication; extensive timing and power characterizations will be presented in the final paper.